1. Field of the Invention
The present invention relates to flash memory devices, and more particularly, to a flash memory device using an error correction code (ECC) algorithm.
2. Description of the Related Art
The demand for flash memory devices, which are nonvolatile memory devices, has increased with the popularity of mobile computer systems, cell phones, MP3 players and various other consumer electronics. A flash memory device is electrically programmable and erasable, and can retain data even if power supply is interrupted.
Flash memory devices include NOR flash memory devices and NAND flash memory devices which have different methods of connecting memory cells with bit lines. In general, the NOR flash memory devices have the disadvantage that they require large currents. In comparison, the NAND flash memory devices require smaller cell currents than the NOR flash memory devices.
FIG. 1A is a circuit diagram of a NAND cell including a plurality of memory cells included in a conventional NAND flash memory device, and FIG. 1B is a circuit diagram of a plurality of memory cells in a conventional NOR-type flash memory device.
Referring to FIG. 1A, the conventional NAND flash memory device may include a plurality of memory cells M11 to M14 connected to word lines WL11 to WL14, respectively. The memory cells M11 to M14 together with selection transistors ST1 and ST2 constitute a NAND “string” structure. In contrast, referring to FIG. 1B, the conventional NOR flash memory device includes a first plurality of memory cells M21 to M23 connected in parallel to bit line BL1 and a common source line CSL. A second plurality of memory cells M24 to M26 are connected in parallel to bit line BL2 and a second common source line CSL. Since the NAND flash memory device (FIG. 1A) requires a smaller cell current, all memory cells connected to a single word line may be programmed at the same time. In contrast, since the NOR flash memory device requires a large current, only a predetermined number of memory cells may be programmed during a program operation.
As compared with other recording media such as hard disks, flash memory devices are highly reliable. In general, a failure occurs in at most one memory cell per write unit (e.g., per page unit). Accordingly, the manufacturers of flash memory devices are adopting error correction code (ECC) algorithms in order to correct data read from a defective memory cell during a read operation. For example, there are many cases where flash memory devices adopt ECC algorithms based on the Hamming codes, which are capable of detecting and correcting an 1-bit error in one error correction code (ECC) unit.
FIG. 2 is a block diagram of a cell array of a conventional flash memory device using an ECC algorithm.
Referring to FIG. 2, a memory cell array 10 includes data memory cells 11 for storing data and a parity memory cell 12 for storing a parity code required to correct an error. During a read operation, the parity code stored in the parity memory cell 12 is also read and transmitted to a block that performs the ECC algorithm. In order to increase a read efficiency, the conventional flash memory device is configured such that the data memory cells 11 share a bulk (active region) with the parity memory cell corresponding to the data memory cell 11.
A NAND flash memory device erases the memory cell array 10 before data is written therein. When the data memory cells 11 share the bulk with the parity cell 11, data stored in the data memory cells 11 may be erased along with a parity code stored in the parity cell 12. Thus, the parity code stored in the parity cell 12 cannot be used during an erase operation of the flash memory device, so that the ECC algorithm cannot be applied to the erase operation.
Conventionally, during the erase operation of the flash memory device threshold voltages of all the data memory cells 11 are controlled to be lower than a predetermined voltage. Also, after the erase operation, it is verified whether there is a data memory cell 11 whose threshold voltage is not lower than the predetermined voltage, and the erase operation is repeated until the threshold voltages of all the data memory cells 11 are sufficiently low. In that case, the erase operation is repeated even if a 1-bit error occurs in one error correction code (ECC) unit. As a result, when the threshold voltage of any one memory cell is not properly controlled, the entire erase operation may be failed, and an erase time may be increased due to repetition of the erase operation.